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vishay siliconix SIP11206 document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 1 half-bridge controller with pr imary mosfet drivers for intermediate bus converters features ? 36 v to 75 v input voltage range ? withstand 100 v, 100 ms transient capability ? integrated 1.6 a typical high- and low-side mosfet drivers ? oscillator frequency is programmable from 200 khz to 1 mhz and can be externally synchronized ? high voltage pre-regulator operates during start-up ? current sensing on primary low-side switch ? hiccup mode ? system low input voltage detection ? chip uvlo function ? programmable soft-start function ? over temperature protection (160 c) ? greater than 95 % efficiency applications ? intermediate bus architectures ? telecom and datacom ? routers and servers ? storage area network ? base station ? 1/8 and 1/4 bricks description SIP11206 is a controller for the primary side of a half-bridge intermediate bus converter (ibc). it is ideally suited for isolated applications such as telecom, data communications and other products requiring an ibc architecture and conversion of standard bus voltages such as 48 v to a lower intermediate voltage, where high efficiency is required at low output voltages (24 v, 12 v, 9 v or 5 v). designed to operate within the telecom voltage range of 36 v to 75 v and withstand 100 v transients for a period of 100 ms, the ic is designed for controlling and driving both the low- and high-side switching devices of a half-bridge converter. the SIP11206 operates with a fixed duty cycle to provide the highest efficiency over a wide input voltage range. SIP11206 has advanced current monitoring and control circuitry, which allows the user to set the maximum current in the primary circuit. this feature acts as protection against overcurrent, output short circuit. current s ensing is by means of a sense resistor connected in series with the primary low-side mosfet. typical application circuit si2303bds si2303bds si7456dp si7456dp si7 8 4 8 dp si7 8 4 8 dp v o- v in+ v o+ v in- v i n det 1 v i n 2 v cc 3 comp 4 cs 5 ag n d 6 v ref 7 r osc 8 bst 16 dh 15 lx 14 dl 13 pg n d 12 ss 11 r db 10 c osc 9 SIP11206 36 v to 75 v 100 v/100 ms r db
www.vishay.com 2 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 technical description SIP11206 is a switching controll er on the primary side of a half-bridge intermediate bus converter. with 100 v depletion mode mosfet in the chip, the SIP11206 is capable of being powered directly from the high voltage bus to v cc through an external pnp pass transistor, or may be powered by an external supply directly to the v cc pin. without the use of an external pass transistor, failure of the converter output to power v cc above the v reg level will result in over temperature protection activating hiccup operation whenever the pre-regulator power dissipation becomes excessive. the external high- and low-side n-channel power mosfets are driven by a built in driver with 1.6 a peak current capability. SIP11206 is available in the mlp44-16 powerpak ? package and tssop-16 powerpak ? package and is specified over the ambient temperature range of - 40 c to + 85 c SIP11206 block diagram le v el shift pre reg dri v er control osc p w m comp hi-side dri v er lo w -side dri v er otp v i n v cc r osc v ref pg n d ss ram p bst dh lx dl u v lo o v er c u rrent protection cs + - ag n d v i n det v cc 0.13 v c osc i dss i ss + - 0. 8 5 v ss 4. 8 v le le e n v ref e n e n i ss 250 m v + - i dss e n i bias d max comp r db v ref i bias v sd e n 0.200 v e n + - v u v v u v bg + ss comp v reg
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 3 vishay siliconix SIP11206 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 25.6 mw/c above 25 c. c. derate 26.3 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. absolute maximum ratings all voltages referenced to gnd = 0 v parameter limit unit v in , v lx continuous 80 v 100 ms 100 v cc 14.5 v bst continuous 95 100 ms 112 v bst - v lx 15 logic inputs - 0.3 to v cc + 0.3 linear inputs - 0.3 to v cc + 0.3 hv pre-regulator input current (continuous) 10 ma storage temperature - 65 to 150 c maximum junction temperature 150 power dissipation powerpak mlp44-16 a ,b 2564 mw powerpak tssop-16 a, c 2630 thermal impedance ( ja ) powerpak mlp44-16 a ,b 39 c/w powerpak tssop-16 a, c 38 recommended operating range all voltages referenced to gnd = 0 v parameter limit unit v in continuous 36 to 75 v 100 ms 100 v bst v in + 10.5 to v in + 13.2 v bst - v lx 10.5 to 13.2 v cc 10.5 to 13.2 logic inputs - 0.3 to v cc + 0.3 linear inputs - 0.3 to v cc + 0.3 f osc 200 to 1000 khz r osc 40 to 200 k c osc 100 to 220 pf c ss 10 to 100 nf c comp 2.2 v ref capacitor to gnd 1 f c boost 0.1 v cc capacitor to gnd 4.7
www.vishay.com 4 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 specifications parameter symbol test conditions unless otherwise specified t a = - 40 c to + 85 c, f osc = 800 khz, 10.5 v v cc 13.2 v, v indet = 4.8 v, v in = 48 v, r db = 47.5 k , r osc = 47.5 k , c osc = 100 pf limits unit min. typ. max. pre-regulator v in range v in 36 48 75 v pre-reg current (cut-off) i vinlkg v in = 75 v, v cc > 10.5 v 10 a pre-reg current (standby) i vinsd v in = 75 v, v indet = 0 v 90 200 pre-reg current (switching) i vinsw v in = 75 v, v indet = 7.5 v 3.3 6.0 8.7 ma pre-reg output voltage v reg v cc voltage with v in = 48 v 7.8 9.3 10.4 v pre-reg drive current i start v cc < v reg 20 ma pre-reg load regulation ldr i load : 0 to 20 ma 100 mv pre-reg line regulation lnr 0.05 %/v regulator compensation i src v cc = 12 v - 35 - 20 - 10 a i snk 40 87 130 v cc supply voltage v cc range v cc 10.5 12 13.2 v shut down current i sd v indet = 0 v 50 150 350 a quiescent current i q v indet < v ref 4.0 5.0 6.2 ma supply current i cc v indet > v ref 5.5 7.2 9.5 uvlo off-threshold uvlo h v cc rising 7.6 9.0 10 v hysteresis h uvlo 1.2 v cc clamp voltage v clamp force 20 ma into v cc 14 15.3 16.2 current sense current limit threshold 1 (moc) a v moc i ss = 20 a, c ss = 1 nf 105 130 160 mv current limit threshold 2 (soc) b v soc i ss = 400 na, c ss = 1 nf 165 200 235 cs to dl delay t d 150 ns leading edge blanking period t bl dl (on) blanking time 20 pulse width modulator maximum duty cycle c d max 47 50 % maximum duty cycle asymmetry 1 r db voltage v rdb 3.18 v oscillator oscillator frequency d f osc r osc = 47 k , c osc = 100 pf 680 800 920 khz oscillator bias voltage v rosc 3.24 v soft start soft start charging current i ss v ss = 0 v - 26 - 20 - 14 a ss ramp completion voltage v ss 5.4 v moc discharge current i dss1 cs = v moc 14 20 26 a soc discharge current i dss2 cs = v soc 400 na reset voltage v ssl cs < v moc 0.25 v reference output voltage v ref v cc = 12 v 3.2 3.3 3.4 v short circuit current i refsc v ref = 0 v - 50 - 42 ma load regulation v r / i r (0 ma i load 2.5 ma) - 33 - 16 mv
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 5 vishay siliconix SIP11206 notes: a. moc stands for moderate overcurrent voltage at cs pin. b. soc stands for severe overcurrent voltage at cs pin. c. r db should be chosen for each application to prov ide adequate dead time. for production testing r db is chosen to test at 47 % target duty. d. not tested. guaranteed by driver frequency test. the driver frequency is half of the oscillator frequency. specifications parameter symbol test conditions unless otherwise specified t a = - 40 c to 85 c, f osc = 800 khz, 10.5 v v cc 13.2 v, v indet = 4.8 v, v in = 48 v, r db = 47.5 k , r osc = 47.5 k , c osc = 100 pf limits unit min. typ. max. v indet function v indet pin input impedance r indet 30 46 70 k shutdown threshold high voltage v sdh v indet rising 0.33 0.58 0.76 v shutdown hysteresis voltage h sd 0.15 under voltage off voltage v uvh v indet rising at i cc 3.14 3.30 3.46 under voltage hysteresis voltage h uv 0.26 over temperature protection (otp) activating temperature otp on t j rising 160 c de-activating temperature otp off t j falling 145 high-side mosfet driver (dh output) output high voltage (differential) v dhh sourcing 10 ma, v dh - v bst - 0.3 v output low voltage (differential) v dhl sinking 10 ma, v dh -v lx 0.3 peak output sourcing current i dhh v cc = 10.5 v, c load = 3 nf - 2.2 a peak output sinking current i dhl 1.6 driver frequency f dh 340 400 460 khz rise time t hr c load = 3 nf 20 ns fall time t hf c load = 3 nf 20 boost pin current (switching) i bst v lx = 75 v, v bst = v lx + v cc 1.3 2.6 3.9 ma lx pin current (switching) i lx - 2.1 - 1.4 - 0.7 lx pin leakage current i lx-lkg v indet = 0 v, v lx = 40 v 10 a low-side mosfet driver (dl output) output high voltage (differential) v dlh sourcing 10 ma, v dl - v cc - 0.3 v output low voltage (differential) v dll sinking 10 ma, v dl - v agnd 0.3 peak output sourcing current i dlh v cc = 10.5 v, c load = 3 nf - 1.6 a peak output sinking current i dll 1.6 driver frequency f dl 340 400 460 khz rise time t lr c load = 3 nf 20 ns fall time t lf c load = 3 nf 20
www.vishay.com 6 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 package and pin configuration notes: for mlp44-16 package the bottom pin 1 indi cator is connected to epad or agnd. to p v ie w 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top v ie w 1 v cc comp cs ag n d r osc c osc r db v ref ss pg n d dl lx dh bst v i n det v i n mlp44-16 powerpak packa g e tssop-16 powerpak packa g e tssop-16 mlp44-16 symbol description 31 v cc pre-regulator output and supply voltage for internal circuitry 4 2 comp pre-regulator compensation pin 5 3 cs current sense comparator input 6 4 agnd analog ground (connected to package?s exposed pad) 75 v ref 3.3 v reference output and bypas s capacitor connection pin 86 r osc oscillator resistor connection 97 c osc oscillator capacitor connection and external frequency sync. connection 10 8 r db dead time setting resistor connection 11 9 ss soft start capacitor connection 12 10 pgnd power ground 13 11 dl primary low-side mosfet drive signal 14 12 lx high-side mosfet source and transformer connection node 15 13 dh primary high-side mosfet drive signal 16 14 bst bootstrap voltage pin for the high-side driver 115 v indet shut down/under voltage/enable control pin 216 v in high voltage pre-regulator input ordering information part number package marking temperature SIP11206dqp-t1-e3 tssop-16 11206 - 40 c to + 85 c SIP11206dlp-t1-e3 mlp44-16
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 7 vishay siliconix SIP11206 timing diagram and soft start duty cycle control hiccup response to moderate overcurrent faults over current protection operation showing reduction in duty cycle down to the hiccup trigger point. ss continues to discharge down to 250 mv (400 na i discharge ), and then will recharge at 20 a. r db d max. time c osc ss dl dh ss clamp le v el dl dh cs i n clk hicc u p triggered d max. clamp le v el hicc u p trigger le v el ss oc_det
www.vishay.com 8 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 circuit for frequency synchronization detailed operational description start up the controller supply (v cc ) is linearly regulated up to its target voltage v reg by the on chip pre-regulator circuit. during power up with v indet ramping up from 0, the v cc capacitor minimum charge current is 20 ma and the pre-regulator voltage is typically 9.3 v. as v indet exceeds v ref , the dl/dh outputs are capable of driving 3 nf mosfet gate capacitances and hence the pre-regulator load regulation can easily handle 120 a to 20 ma load step with a typical load regulation of 1 %. current into the external v cc capacitor is limited to typically 20 ma by the internal pre-regulator unless an external power source is connected to v cc pin. this source may be a dc supply or from v in by connecting a pnp pass transistor between v in and v cc . the v cc pin is protected by a 20 ma clamp when this pin exceeds 14.5 v. the clamp turns on when v cc is between 14.5 v and 16 v. when v cc exceeds the uvlo voltage (uvlo h ) a soft start cycle of the switch mode supply is initiated. the v cc supply continues to be charged by the pre-regulator until v cc equals v reg . during this period, between uvlo h and v reg , excessive load may result in v cc falling below uvlo h and stopping switch mode operation. this situation is avoided by the hysteresis between v reg and uvlo off-threshold level uvlo l . pwm operation during startup, dl always turns on before dh and both switch on and off at half the oscillator frequency. the driver duty cycle increases as ss voltage increases, since the ss comparator sets the on puls e width by comparing the ss ramp voltage with the oscillator ramp voltage. when ss ramp reaches a voltage that equals to r db voltage, the pwm comparator, which compares r db voltage to the oscillator ramp, takes over and the ma ximum duty cycle is now set by the oscillator ramp and r db voltage. mathematically, the total duty cycle is determine d by the following formula: d total = r db /r osc and the duty cycle on dl or dh will be approximately half of d total . please note that due to oscillator comparator overshoot the exact duty cycl e calculated using above formula may be slightly differ ent. the pwm operation during start up can be better understood by referring to "timing diagram and soft start duty cycle control" graph. the soft start completion voltage at ss pin is clamped above the internal ramp waveform's upper turning point. soft start the soft start circuit plays an im portant role in protecting the controller. at startup it preven ts high in-rush current. during a normal start-up sequence (v cs < v moc . v cs is the voltage at cs pin), or following any event that would cause a hiccup- and-soft-start sequence, c ss will be charged from about 0 v to a final voltage of 4.8 v at a 20 a rate. as the voltage on the c ss rises towards the final voltage, the maximum permitted dl and dh duty cycles will increase from 0 % to a maximum defined by the r db resistor. when a mild fault condition is detected (v cs = v moc ), c ss goes into a hiccup mode until fault condition is removed. the hiccup is activated when c ss discharges to 0.85 v ss at 20 a and subsequently at 0.4 a until the fault condition is removed. refer to "fault conditions and responses" for details. fault conditions and responses the faults that can cause a hiccup-and-retry cycle are moderate over-current (moc), severe over-current (soc), chip level uvlo, system level uvlo, and over temperature protection (otp). prior to detailing the various fault conditions and responses, some definitions are given: 1. a complete switching period, t, consists of two oscillator cycles, t dl and t dh . 2. t dl (t dh ) is the oscillator cycle during which the dl (dh) output is in the high state. 3. t is defined as starting at the beginning of t dl , and terminating at the end of t dh . response to moc faults (v moc < v cs < v soc ): once SIP11206 has completed a normal soft-start cycle, v ss will be clamped at 4.5 v, allowing the maximum possible duty cycle on dl and dh. 220 pf SIP11206 c osc 100 1 k sy n c i n 2 n 3904
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 9 vishay siliconix SIP11206 if an moc fault occurs following the start-up (due to a condition such as an excessive load on the converter?s output), SIP11206 will respond by gradually reducing the available maximum duty cycle of its dl and dh outputs each to be equal to approximately 42 % of their possible 47 % maximum values. this is before any effects of deadtime introduced by r db are added in. this reduction in available maximum duty cycle is achieved by reducing the voltage on the ss pin to 4 v, as follows: 1. if v moc < v cs < v soc at any time during t dl , a current of 20 a will be drawn out of the ss pin until the beginning of the next t dl . 2. if the voltage on the ss pin remains above the value that would allow an available ma ximum dl and dh duty cycle of 42 %, SIP11206 will continue operating. 3. if the voltage on the ss pin goes below the value that would allow an available ma ximum dl and dh duty cycle of 42 %, a hiccup interval is started, during which both dl and dh are held in their low states. 4. the ss pin is discharged towards 0 v by a 400 na sink current. 5. the hiccup interval is terminated when the ss pin is discharged to 0.25 v. after the above actions have been taken switching on the dl and dh outputs will then resume with a normal soft-start cycle. response to moc faults is enabled after the successful completion of any no rmal soft-start cycle. response to soc faults (v cs > v soc ): this is an immediate, singl e-cycle response over current shutdown, followed by a hiccup delay and a normal soft-start cycle. since this is a gross fault protection mechanism, its triggering mechanism is asynchronous to the timing of t dl and t dh . 1. if v cs > v soc , a hiccup interval is started, during which both dl and dh are held in their low states. 2. the ss pin is discharged towards 0 v by a 400 na sink current. 3. the hiccup interval is terminated when the ss pin is discharged to 0.25 v. 4. switching on the dl and dh outputs will then resume with a normal so ft-start cycle. severe over current response is enabled at all times, including the initial ramp-up peri od of the soft-start pin. this allows SIP11206 to provide rapid fault protection for the converter?s power train. immediate response to uvlo faults: the under voltage protection co nditions at converter-level (v indet pin uvlo) and chip-level (v cc uvlo) will immediately trigger a shutdown-and-retry ss response, with the restart requir ements being that: 1. the ss pin has been discharged at a 20 a rate to the 0.25 v level. 2. the affected supply has recovered to its turn-on threshold. once these conditions are met, switching will resume with a normal soft-start cycle. response to uvlo faults is enabled at all times, including the initial ramp-up period of the soft- start pin. immediate response to an otp condition: failure of the application circuit to provide an external voltage to the v cc pin above the v reg level may result in an otp condition (t j > otp on ). other conditions, such as excessive ambient temperature or, where applicable, failure of airflow over the dc-dc converter circuit, can also trigger an otp condition. an otp condition will immediately trigger a shutdown-and-retry soft start response, with the restart requirements being that: 1. the ss pin has been discharged at a 20 a rate to the 0.25 v level. 2. the chip junction temperature has fallen below the lower otp threshold. once these conditions are met, switching will resume with a normal soft-start cycle. response to the otp condition is enabled at all times, including the initial ramp-up period of the soft-start pin. reference the reference voltage of SIP11206 is set at 3.3 v at v ref pin. this pin should be decoupl ed externally with a 0.1 f to 1 f capacitor to gnd. up to 5 ma may be drawn internally from this reference to power external circuits. note that if the v indet pin is pulled below 0.55 v (typical), the reference will be turned off, and SIP11206 will enter a low-power "standby" mode. during startup or when v ref is accidentally shorted to ground, this pin has internal sh ort circuit protection limiting the source current to 50 ma. v ref load regulation for 5 ma step is typically 0.45 %. oscillator the oscillator is designed to operate from 200 khz to 1 mhz with temperature stability wit hin 15 %. this operating frequency range allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. the oscillator frequency, and therefore the switching frequency, is pr ogrammable by the value of resistor and capacitor connected to the r osc and c osc pins respectively. note that the switching frequency at pins dl and dh is half of the oscillator frequency, i.e., the dl output will be active during one osci llator cycle, and the dh during the next oscillator cycle. v indet the v indet pin controls several modes of operation and the modes of operation are controlled by shutdown (v sd ) and under voltage (v uv ) comparators (see block diagram). when the ic is powered solely by v in and v indet is less than v sdh
www.vishay.com 10 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 due to some external reset condition the pre-regulator is in low power standby mode and the internal bias network is powered down. when v indet is greater than v sdh but less than v ref and v cc is forced to 12 v the pre-regulator shuts off drawing only leakage current from v in and quiescent current from v cc . in this mode the cont roller output drivers remains static (non-switching). when v indet is above v ref the controller is enabled and both drivers are switching at half the oscillator frequency. if SIP11206 is shut down via this pin, its restart will be by means of a soft-start cycle, as described under "soft start" and "hiccup-mode operation" above. the input impedance to ground of this pin is typically 46k 30 % and must be taken into account at application design. an external 10:1 resistor divider ratio of supply voltage to v indet pin is required in a typical application. primary high and low side mosfet drivers the low-side mosfet driver is powered directly from v cc of the chip. the high-side mosfet however requires the gate voltage to be higher than v in . this is achieved with a charge pump capacitor c bst between bst and lx, and an external diode to charge and bootstrap the initial charge up voltage across c bst to v cc level. on the alte rnate oscillator cycle the boost diode isolates bst from v in and hence bst and lx steps up to v in + v cc and v in , respectively. this sequencing insures that dl will always turn on before dh during start-up. the boost capacitor value must be chosen to meet the application droop rate requirement. external frequency synchronization the oscillator frequency of this ic can be synchronized to an external source with a simple circuit shown in "circuit for frequency synchronization" diagram. the synchronized frequency should not exceed 1.4 times the set frequency, and the synchronized frequency range should not exceed the ic frequency range. typical characteristics v reg vs. temperature v uv vs. temperature temperat u re (c) v reg ( v ) 8 .2 8 .4 8 .6 8 . 8 9.0 9.2 9.4 9.6 9. 8 10.0 10.2 - 40 - 15 10 35 60 8 5 110 135 - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) v u v ( v ) 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 v u v h v u v l i vin vs. temperature i cc and i q vs. temperature temperat u re (c) i v i n (ma) - 40 - 15 10 35 60 8 5 110 135 4.5 5.0 5.5 6.0 6.5 7.0 7.5 v i n = 75 v temperat u re (c) i cc, i q (ma) - 40 - 15 10 35 60 8 5 110 135 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8 .0 i cc v cc = 12 v i q
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 11 vishay siliconix SIP11206 typical characteristics v sd vs. temperature uvlo vs. temperature i dss1 vs. temperature - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) v sd (m v ) 200 300 400 500 600 700 8 00 v sdh v sdl 7.5 8 .0 8 .5 9.0 9.5 10 - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) u v lo ( v ) u v lo h u v lo l - 40 - 15 10 35 60 85 110 135 temperature (c) i dss1 (a) 15 16 17 18 19 20 21 22 23 i sd vs. temperature v ss vs. temperature i ss vs. temperature temperat u re (c) i sd ( a) - 40 - 15 10 35 60 8 5 110 135 8 0 100 120 140 160 1 8 0 200 - 40 - 15 10 35 60 85 110 135 temperature (c) v ss (v) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 - 40 - 15 10 35 60 85 110 135 temperature (c) i ss (a) - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15
www.vishay.com 12 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 typical characteristics i dss2 vs. temperature f dl /f dh vs. temperature v ref vs. temperature - 40 - 15 10 35 60 85 110 135 temperature (c) i dss2 (a) 0.30 0.35 0.40 0.45 0.50 0.55 - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) freq (khz) 370 3 8 0 390 400 410 420 430 f dl f dh temperat u re (c) v ref ( v ) 3.2 88 3.290 3.292 3.294 3.296 3.29 8 3.300 3.302 3.304 - 40 - 15 10 35 60 8 5 110 i vinsd vs. temperature d max. vs. temperature v rdb vs. temperature temperat u re (c) i v i n sd ( a) - 40 - 15 10 35 60 8 5 110 135 0 20 40 60 8 0 100 120 140 - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) d max ( % ) 45.6 45. 8 46.0 46.2 46.4 46.6 46. 8 47.0 47.2 47.4 dh = 40 v dl = 44 v temperat u re (c) v rdb ( v ) - 40 - 15 10 35 60 8 5 110 135 3.15 3.16 3.17 3.1 8 3.19 3.20 v cc = 12 v
document number: 69232 s-81795-rev. c, 04-aug-08 www.vishay.com 13 vishay siliconix SIP11206 typical characteristics dl r dsn vs. temperature dh r dsn vs. temperature v cs vs. temperature - 40 - 15 10 35 60 85 110 135 temperature (c) r dsn ( ) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 - 40 - 15 10 35 60 85 110 135 temperature (c) r dsn ( ) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) v cs (m v ) 100 125 150 175 200 225 v soc v moc dl r dsp vs. temperature dh r dsp vs. temperature r vindet vs. temperature - 40 - 15 10 35 60 8 5 110 135 temperat u re (c) r dsp ( ) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 - 40 - 15 10 35 60 85 110 135 temperature (c) r dsp ( ) 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 - 40 - 15 10 35 60 85 110 135 temperature (c) r vindet (k ) 35 40 45 50 55 60 65
www.vishay.com 14 document number: 69232 s-81795-rev. c, 04-aug-08 vishay siliconix SIP11206 typical characteristics typical waveforms vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?69232 . line and load regulation 8 9 10 11 12 13 14 03691215 load c u rrent (a) o u tp u t v oltage ( v ) v i n = 55 v v i n = 4 8 v v i n = 42 v efficiency vs. current 8 0 8 4 88 92 96 0 3 6 9 12 15 load c u rrent (a) efficiency ( % ) v i n = 55 v v i n = 4 8 v v i n = 42 v system startup system shutdown primary driving signals dl and dh hiccup mode when output shorted
detail a c l c l c l 0.07600 0.025 ? 0.075 dp pin 1 indicator polish c l 0.7500 3 c bbb m b c aaa 4 8 d 6 n e e1 e 8 7 ? b ? e 123 0.7500 top view c l 9 b b detail a l1 l gauge plane r1 r ? h ? seating plane 1 0.25 exposed pad bottom view s a s ? c ? b ? a ? 7 a1 a2 ccc s seating plane a c (b) 5 b1 c1 detail b-b x y package information vishay siliconix document number: 72778 31-mar-05 www.vishay.com 1 of 2 power ic thermally enhanced powerpak tssop: 14/16-lead
notes: 1. all dimensions are in millimeters (angles in degrees). 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. 4. dimension ?e1? does not include internal flash or protrusion. 5. dimension ?b? does not include dambar protrusion. 6. ?n? is the maximum number of lead terminal positions for the specified package length. 7. datums ? a ? and ? b ? to be determined at datum plane ? h ? . 8. dimensions ?d? and ?e1? are to be determined at datum plane ? h ? . 9. cross section b-b to be determined at 0.10 to 0.25 mm from the lead tip. 10. refer to jedec mo-153, issue c., variation abt. 11. exposed pad will depend on the pad size of the l/f. package information vishay siliconix www.vishay.com 2 of 2 document number: 72778 31-mar-05 power ic thermally enhanced powerpak tssop: 14/16-lead millimeters inches* dim min nom max min nom max a ? ? 1.20 ? ? 0.0472 a 1 0.025 ? 0.100 0.001 ? 0.0039 a 2 0.80 0.90 1.05 0.0315 0.0354 0.0413 b 0.19 ? 0.30 0.0075 ? 0.0118 b1 0.19 0.22 0.25 0.0075 0.0087 0.0098 c 0.09 ? 0.20 0.0035 ? 0.0079 c1 0.09 ? 0.16 0.0035 ? 0.0063 d 4.9 5.0 5.1 0.1929 0.1968 0.2008 e 0.65 bsc 0.0256 bsc e 6.2 6.4 6.6 0.2441 0.2520 0.2598 e 1 4.3 4.4 4.5 0.1693 0.1732 0.1772 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.0 ref 0.0394 ref r 0.09 ? ? 0.0035 ? ? r1 0.09 ? ? 0.0035 ? ? 1 0 ? 0 0 ? 0 n (14) 14 14 n (16) 16 16 x 2.95 3.0 3.05 0.116 0.118 0.120 y (14) 3.15 3.2 3.25 0.124 0.126 0.128 y (16) 2.95 3.0 3.05 0.116 0.118 0.120 aaa 0.10 0.0039 bbb 0.10 0.0039 ccc 0.05 0.0020 ddd 0.20 0.0079 ecn: s-50568?rev. b, 04-apr-05 dwg: 5913 *dimensions are in mm converted to inches.
terminal tip 5 index area (d 2 e 2) l e2/2 e2 detail a 2 1 n-1 n (nd-1) x e 8 bottom view c bbb m a b n b 5 datum a or b n r e terminal tip 5 even terminal/side odd terminal/side detail b e e/2 4 c aaa 2 x package information vishay siliconix document number: 72802 16-may-05 www.vishay.com 1 powerpak mlp44-16 (power ic only) jedec part number: mo-220
notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. all angels are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 iden tifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a molded or marked feature. the x and y dimens ion will vary according to lead counts. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. 6. nd and ne refer to the number of terminals on the d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. variation hhd is shown for illustration only. 9. coplanarity applies to the exposed heat sink slug as well as the terminals. package information vishay siliconix www.vishay.com 2 document num ber: 72802 16-may-05 powerpak mlp44-16 (power ic only) jedec part number: mo-220 millimeters* inches dim min nom max min nom max notes a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0 0.02 0.05 0 0.0008 0.0020 a3 ? 0.20 ref ? ? 0.0079 ? aa ? 0.345 ? ? 0.0136 ? aaa ? 0.15 ? ? 0.0059 ? bb ? 0.345 ? ? 0.0136 ? b 0.25 0.30 0.35 0.0098 0.0118 0.138 5 bbb ? 0.10 ? ? 0.0039 ? cc ? 0.18 ? ? 0.0071 ? ccc ? 0.10 ? ? 0.0039 ? d 4.00 bsc 0.1575 bsc d2 2.55 2.7 2.8 0.1004 0.1063 0.1102 dd ? 0.18 ? ? 0.0071 ? e 4.00 bsc 0.1575 bsc e2 2.55 2.7 2.8 0.1004 0.1063 0.1102 e 0.65 bsc 0.0256 bsc l 0.3 0.4 0.5 0.0118 0.0157 0.0197 n 16 16 3, 7 nd ? 4 ? ? 4 ? 6 ne ? 4 ? ? 4 ? 6 r b(min)/2 ? ? b(min)/2 ? ? * use millimeters as the primary measurement. ecn: s-50794?rev. b, 16-may-05 dwg: 5905
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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